This guide is for PCB designers, hardware engineers, and layout engineers who need to size traces for current without treating a calculator result as a finished spec. It explains how copper weight, inner versus outer layers, allowable temperature rise, and etch change current capacity, voltage drop, and cost, and how to write those choices so fabrication does not guess.
This guide is for PCB designers, hardware engineers, and sourcing leads who specify 2 oz copper and need to stop treating that weight as finished thickness. It separates nominal foil from plated outer copper, explains when 2 oz is justified versus 1 oz or 0.5 oz, and shows how to write stack-up notes so current, impedance, etch, and quotes stay aligned.
This guide is for PCB designers, hardware engineers, and sourcing leads who treat “1 oz” as a finished number. It separates nominal foil from finished 1 oz copper thickness, shows why inner and outer layers do not finish the same, and walks through stack-up, trace-width, and fabrication-note decisions so the board that is quoted is the board that is built.
For PCB designers, hardware engineers, and sourcing leads who specify copper on a drawing. This guide separates nominal copper weight from finished copper thickness, explains why inner and outer layers do not finish the same, and shows how to write a callout the fabricator can build without guessing.
Hardware engineers, PCB designers, and power-electronics teams often treat the board as a passive carrier. This guide treats PCB thermal resistance as a design variable: how materials, copper planes, and thermal vias move heat from a pad toward a rejection path. Use it to match copper weight, via strategy, and substrate to power density—without assuming extra copper will cool the design.
This guide is for hardware engineers, PCB designers, and SI/PI teams planning multilayer boards. It corrects the habit of treating stack-up as only layer count and finished thickness. You will work through layer roles, material and dielectric choices, copper weight and balance, and impedance planning with a fabricator so the stack supports return paths, power integrity, and repeatable production.
This guide is for hardware engineers, PCB designers, and mechanical or NPI teams defining board outline and stack-up. It corrects the habit of treating thickness as an afterthought and covers common FR-4 values, connector and enclosure fit, warpage, and stack-up. Use it to lock a standard thickness—or to specify a non-standard value with the right trade-offs in view.